Advances in techniques for packaging semiconductor die are being driven by the market for smaller, lower cost electronic devices with increasing functionality. Chip scale packaging (CSP) encompasses a number of different packaging techniques where the size of the packaged die is only slightly larger than the size of the die itself (e.g. a ratio of areas which does not exceed 1.2:1). In one example of CSP, the die may be mounted onto a package on which solder balls (or bumps) are formed (e.g. a ball grid array package), such that the die is electrically connected to the package by means of wirebonds and the assembled package may be mounted onto a printed circuit board (PCB) using BGA techniques or flip-chip bonding.
In wafer level chip scale packaging (WLCSP), also referred to as wafer level packaging, the solder balls (or bumps) are formed directly on the semiconductor wafer, before the wafer is diced into individual die. This results in a very compact packaged die and enables wafer scale testing of packaged die, which may have cost and efficiency benefits.